I'm having some trouble with a streaming interface that I've set up for a short message passing application. The interface is a byte wide Xillybus stream, connected to a FIFO in the FPGA. The messages which are failing are quite short, 2 or 3 bytes. I've tried this with both synchronous and asynchronous core options.
About 50% of the time, the read() call to the interface does not return; however, I've instrumented the FIFO interface with chipscope (or whatever the Vivado version is called) and confirmed that the FIFO is being completely read to empty on every access, regardless of whether or not read() returns. What is quite curious is that, even if the read call only requests one byte, all 2-3 bytes will be read from the FIFO. Is this expected behaviour for both synchronous and asynchronous access? Does the short message size explain why read hangs? Are there any options for the core that may fix this?