Hello,
I'm new to FPGA. I'm trying the bundle demo for Xilinx VC709 Board with Vivado 2017.2 on Windows7.
I'm following the Xillybus demo guide with using blockdesign.
I am using stream read and write to transfer files(32bit) from host PC, process in the FPGA and send the data back (just loop back test).
I found the front data loop back can get the same value. But the other data loop back cause different value.
I need to guarantee data from host to FPGA can always be correct.
How can I do?
Greatly appreciate for any help in advance!
Thanks,
James