1) For the signal "user_r_{devfile}_eof" , could you elaborate the following sentences ? Besides, why is the signal user_r_read_32_eof assigned as 0 in the demo bundle ?
Like the ’empty’ signal, the ’eof’ signal must be asserted only on a clock cycle following a read cycle. An exception for this is when the ’empty’ signal is already asserted, in which case ’eof’ may be asserted at any clock cycle. This exception can be used to make a blocking read() call at the host return immediately. So, one way to assure that ’eof’ is asserted correctly, is to have it combinatorically ANDed with the ’empty’ signal.
2) Do you have examples of why
The ’empty’ signal may and may not be asserted in conjunction with an ’eof’ assertion.
3) How do I see the following as loopback FIFO ?
// 32-bit loopback
fifo_32x512 fifo_32
(
.clk(bus_clk),
.srst(!user_w_write_32_open && !user_r_read_32_open),
.din(user_w_write_32_data),
.wr_en(user_w_write_32_wren),
.rd_en(user_r_read_32_rden),
.dout(user_r_read_32_data),
.full(user_w_write_32_full),
.empty(user_r_read_32_empty)
);