Demo bundle on another Virtex Ultrascale part

[Guest]

Hi,

I have a board with the an XCVU190 FPGA, so I downloaded the bundle for VCU108, and changed the part number in the main.tcl file. Then I ran the Tcl script. When I implemented the project, I got a lot of Critical Warnings:

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CRITICAL WARNING: [IP_Flow 19-3419] Update of 'pcie_ku' to current project options has resulted in an incomplete parameterization. Please review the message log, and recustomize this instance before continuing with your design.


And during syntheses, a lot of Critical Warnings like

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[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[17]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[16]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[15]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[14]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[13]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[12]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[11]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[10]
[Synth 8-4442] BlackBox module \xillybus_ins/pcie  has unconnected pin cfg_mgmt_addr[9]


Digging a bit deeper, I found these in the Tcl log:

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Upgrading 'pcie_ku'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'gen_x0y0' from 'false' to 'true' has been ignored for IP 'pcie_ku'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'gen_x0y2' from 'true' to 'false' has been ignored for IP 'pcie_ku'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'PF0_CLASS_CODE' from '070000' to 'FF0000' has been ignored for IP 'pcie_ku'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'PF1_CLASS_CODE' from '070000' to '058000' has been ignored for IP 'pcie_ku'
WARNING: [IP_Flow 19-3461] Value 'X0Y0' is out of the range for parameter 'PCIe Block Location(pcie_blk_locn)' for IP 'pcie_ku' . Valid values are - X0Y2, X0Y3, X0Y4, X0Y5
WARNING: [IP_Flow 19-3438] Customization errors found on 'pcie_ku'. Restoring to previous valid configuration.
WARNING: [IP_Flow 19-1721] During upgrade of 'pcie_ku':
The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. When checking the upgrade script, note that parameter names are case sensitive.


And also, when I opened the PCIe block's configuration in Vivado, it was configured for lane width 1x Gen1. Many other parameters were completely wrong.

Why does the update of pcie_ku fail? Can anyone help me with this?

[support]

Hello,

Unfortunately, the critical warnings issued by Vivado are a bit misleading. The clue to actual problem is in the Tcl log you posted: The part you're migrating to doesn't have a PCIe block on the site required in the pcie_ku.xci file. Vivado reacts to this by messing up the parameters in general (those related and those which are not).

This leads to enabling certain PCIe features which xillybus.v Verilog module doesn't expect, hence the critical warnings on unconnected pins.

How to solve this: First, figure out the location of the PCIe block that works with the MGTs you intend to use. Alternatively, open the PCIe block's configuration in Vivado, and look at the selected "PCIe Block Location". Even if it's not correct for your board, at least it's a legal site on the targeted FPGA.

Then start from scratch: Unzip a fresh demo bundle, and change the part in main.tcl file, like you did before. But in addition, edit vivado-essentials/pcie_ku/pcie_ku.xci as follows: Find the assignment for PARAM_VALUE.pcie_blk_locn, and change the site to one that is legal for the FPGA. For example, from X0Y0 to X0Y2.

Then run the Tcl script for generating the project. The critical warning on updating pcie_ku should not be there anymore. Vivado will however update additional parameters like MODELPARAM_VALUE.gen_x0y0_xdc and PARAM_VALUE.gen_x0y0 in the XCI file, but this is done properly during the project generation. There's no need to edit these manually.

Note that it's not good enough to make this correction after the project has been created with the Tcl script. The messup of the PCIe block happens when the Tcl script is executed with an illegal site for the PCIe block.

And a final note: What about generating the project and then changing the FPGA part? Exactly the same problem: The PCIe block is automatically locked when the FPGA part is changed. The only way to unlock it is "upgrading" the IP, which leads to the same messup of its parameters. The only difference is that the related warnings are more visible, as they are issued in response to manual actions.

Hope you'll have a smooth run this time.

Regards,
Eli