Problem while integrating two user ipcores with xillybus PCI

[Guest]

In my project I need to implement encryption and decryption algorithms with xillybus PCIe using vivado tools. Since I am new to the FPGA stuff, I am following non-HDL documentation of xillybus PCIe. I successfully implemented encryption ip core and tested using xillybus PCIe. The name of top level function of encryption “xillybus_wrapper” and decryption is “decrpt_wrapper”. When I am including both encryption and decryption ip cores, even my encryption ip core also not working with PCIe. I have read in xillybus website that, the name of the top level function must be always “xillybus_wrapper” and should not be changed. I assume that, the problem is top level function naming. Someone please assist me how to move further if I need to integrate two user logic ip core with xillybus PCIe.

[support]

Hello,

There is nothing special about the name "xillybus_wrapper" except that the example HLS project is set up with that name. As you want two such blocks in your system, you indeed need them to have different names.

You may set up an HLS project from scratch, based upon the example. Or take a fresh example project, and do a Search-Replace of xillybus_wrapper with whatever name you want on all files in it (preferably with some script or something like that). Haven't tried the latter, but I don't see any reason it won't work. It's all text files, after all.

Regards,
Eli