- Code: Select all
mem_reg_16 mem_reg_16 (
.clk (bus_clk ),
.din (user_w_mem_16_data),
.we (user_w_mem_16_wren),
.re (user_r_mem_16_rden),
.addr (user_mem_16_addr ),
.dout (user_r_mem_16_data),
)
[code][/code]
always @(posedge clk) begin
if (we)
mem_reg_16[addr] <= din;
if (re)
dout <= mem_reg_16[addr];
end
In a simple read/write memory interface on xillybus, if I need to delay the `read` and `addr` signal by one clock to improve timing, the `dout` signal will also be delayed by one clock. But in this case, memory cannot be correctly readout through xillybus. I am wondering is there a method to solve this?