Timing constraints fail with XL demo bundle

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Timing constraints fail with XL demo bundle

Postby Guest »

Hello,

I got the XL demo bundle for Kintex-7, and implemented it without any changes on Vivado 2022.1. The timing constraints failed. What should I do?
Guest
 

Re: Timing constraints fail with XL demo bundle

Postby support »

Hello,

All demo bundles are tested on the version of Vivado that was relevant when they were released.

As it turns out, the implementation on Vivado 2022.1 indeed fails timing with a negative slack of 23ps. The path that fails is inside Xilinx' PCIe block (and has a requirement of 2 ns, i.e. 500 MHz), so this problem isn't related to Xillybus. It's unfortunate that a later of version of Vivado fails on Xilinx' own PCIe block where previous versions got it right, but that's the way it is.

It's possible that this problem will go away by itself just by making any modifications to the project. With such a low negative slack, any change can make things both better and worse.

In order to meet the timing constraints with an unmodified demo bundle, this is one of several possible ways: Enter the project's Settings in Vivado's project manager. In the "Implementation" submenu, under "Settings", change the Strategy to Performance_NetDelay_low.

Unfortunately, this disables the showstopper script, which is responsible for preventing the generation of a bitstream if the timing constraints fail. This can be fixed with the following Tcl command:

Code: Select all
set_property STEPS.WRITE_BITSTREAM.TCL.PRE "/full/path/to/demobundle/vivado-essentials/showstopper.tcl" [get_runs impl_1]


(replace the "/full/path/to" with the path, of course)

Regards,
Eli
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