Hi eli,
As I asked in the previous questions. I tried to connect two FIFO together and put a multichannel-FIR between two FIFOs. It works based on your answers! I received the filtered data of multiple channels data that I download into FPGA through xillybus. Thank you!
However, there is still a little bug. My downloaded data is 16bits width and after FIR it becomes 32bits. There is no problem on the reading side, but on the writing side, I still use your 32 bits FIFO and just feed 0-15bits to the FIR module. ( assign fir_in = fifo0_dout[15:0]; )
I thought since my downloaded data is 16bits wide, the w32 steam would pad zeros in the MSB 16bits. But it seems does not work in that way. That actually make me lose half of the data samples which I don't intend to. So what should I do, should I change the FIFO before FIR into a 16bits width FIFO?
Thanks!
Best,
Chongxi