Hi Eli,
As in the previous post, you suggested me how to connect two FIFOs (one FWFT and one regular) and a FIR based on AXI4 stream between these 2 FIFOs.
With that structure, fifo_32_1 receive data from FIR and send data to Xillybus.
fifo_32x512 fifo_32_1
(
.clk(bus_clk),
.srst(!user_r_read_32_open),
.din(tohost),
.wr_en(fir_valid && !fifo1_full), // AXI4 valid and ready
.rd_en(user_r_read_32_rden), // FPGA to CPU
.dout(user_r_read_32_data),
.full(fifo1_full),
.empty(user_r_read_32_empty)
);
Here is a debug data captured by Vivado ILA, which shows the fifo_32_1/din[31:0] captured when fifo_32_1_rd_en asserted.
https://raw.githubusercontent.com/chongxi/KC705_PCIE/master/clock.PNG
It seems that fifo_32_1_rd_en signal is asserted not as regular as fifo_32_1_wr_en.
I understand this rd_en is controlled by the host (user_r_read_32_rden). It seems that some of rd_en signal is longer than others and it does not come with a regular interval. Would this cause any data missing or loss?
Best,
Chongxi