Hi Eli,
So far everything with xillybus is superbly good. When I modify the depth of the `demoarray` inside the xillydemo to 16K. Also I use the customized core with a 32-bits address seeable RAM, so the depth of RAM can be 2^32>>16K. However, there will be a timing fail happen during bitstream generation. The `TPWS` of the `usr_clk1` started to be negative.
Is this due to the fanout of `bus_clk` is not high enough?
I am not sure what does that mean and how to address this. Could you please help giving me some clue?
Best,
Chongxi