Meeting timing constraints
Posted:
Hi,
I have an issue that's been causing me some grief for a few days. I'm hoping someone might have some helpful advice.
I cannot generate a correct bitstream in my project because I have not found a way to handle the timing issues.
Basically, I am sending data to an inferred RAM using the xillybus mem interface. I do not allow one particular register to be written:
Instead this register is updated at each clock cycle (that Read_Enable is not asserted) with the output of a combinational circuit.
Both the above snippets are contained within an always @(posedge bus_clk)
The combinational circuit accepts the other 19 registers as inputs. I want to read the result stored in the 20th array entry back to host. I do not care that the wrong answer will be clocked many times. I will ensure an appropriate delay in the host app.
So my problem is that this does not meet the timing requirements. Do you know what I must do in order to make this idea valid?
Thank you.
I have an issue that's been causing me some grief for a few days. I'm hoping someone might have some helpful advice.
I cannot generate a correct bitstream in my project because I have not found a way to handle the timing issues.
Basically, I am sending data to an inferred RAM using the xillybus mem interface. I do not allow one particular register to be written:
- Code: Select all
if (user_w_mem_8_wren && user_mem_8_addr != 19) begin
array[user_mem_8_addr] <= user_w_mem_8_data;
end
Instead this register is updated at each clock cycle (that Read_Enable is not asserted) with the output of a combinational circuit.
- Code: Select all
if(!user_r_mem_8_rden) begin
array[19] <= result;
end
Both the above snippets are contained within an always @(posedge bus_clk)
The combinational circuit accepts the other 19 registers as inputs. I want to read the result stored in the 20th array entry back to host. I do not care that the wrong answer will be clocked many times. I will ensure an appropriate delay in the host app.
So my problem is that this does not meet the timing requirements. Do you know what I must do in order to make this idea valid?
Thank you.