implement Xillybus on Zynq Ultrascale+ by using petalinux

[zinnc]

Hi, everyone, I want to implement Xillybus on Zynq Ultrascale+ for transfering data between PL and PS.
I checked the content in http://www.xillybus.com/downloads/xillybus_product_brief.pdf, founded that Xillybus do support Zynq Ultrascale+ and AXI bus. So, literally, it certainly can fullfill the duties.
My questions are:
1. In ipfactory, "Target device family" item only includes Zynq7000 series. How to create an Xillybus IP core to support Zynq Ultrascale+ device?
2. How to connect xillybus IP to Zynq PS?
3. Is it possible to use xillybus in non-Xillinux distribution, i.e., one created by Petalinux? If so, should I write custom device-tree file and how can I do that?
Best regards.

[support]

Hello,

Xillybus over PS/PL is supported with Xillinux only, running on a certain set of boards. As for Xillybus' support of Ultrascale+ devices, yes, over the PCIe or USB 3.0 interfaces only.

Since the Xillybus IP core for PL/PS merely relies on the AXI bus, it's indeed possible to port it to any device with an AXI connection between the processor and logic fabric. The IP core itself is the same for all Zynq devices. The reason several options are given at the IP Core Factory is that the xillybus.v wrapper is different. This is just a matter of convenience for easy integration.

Using Xillybus on an unsupported device requires to set up the connection between the IP core and the AXI bus correctly, and in particular set up the attributes of this interface. Also, the system's boot software (FSBL) needs to be implemented to initialize the processor correctly. And then U-boot needs to be set up and compiled. Finally, an entry in the device tree should be added to make Linux detect Xillybus as a peripheral and load its driver. This isn't necessarily a complete list of tasks.

So if you want to try this yourself, I suggest starting from the FPGA Xillinux bundle for Z-Turn Lite, and first try to port Xillybus Lite to your target FPGA. When that works for you, try the main Xillybus core. The idea is to copy the settings from a working design.

How much time this takes depends on your skills, but I can assure you that by the time you've done this, you'll have a deep understanding of the PL/PS interface, the boot process, and the relations between the hardware and software parts.

Of all tasks, working with a different kernel and setting up the device tree is going to be the easiest.

To summarize: Possible, however anything but easy.

Regards,
Eli

[zinnc]

Hi, Eli
Big thanks for your suggestion. I still have some wonder:
1.

The IP core itself is the same for all Zynq devices. The reason several options are given at the IP Core Factory is that the xillybus.v wrapper is different.

Are you suggesting that the IP core file(xillybus_core.ngc) in Xillinux bundle(zturn、zedboard) could be used for ZynqMP as well?
Xilinx ZynqMP only support EDIF file format, is it safe to use NGC2EDIF(ISE tool) for converting netlist?

2. After I checked all the four bundles provied in http://xillybus.com/xillinux, the file size is not the same:
* xillybus_core.ngc in xillinux-eval-zturnlite-2.0d is 1.4MB
* xillybus_core.ngc in xillinux-eval-microzed-2.0d is 1.4MB
* xillybus_core.ngc in xillinux-eval-zedboard-2.0d is 1.8MB
* xillybus_core.ngc in xillinux-eval-zybo-2.0d is 1.8MB
zedboard and zybo are larger because /dev/xillybus_smb and /dev/xillybus_audio logic?
Regards.

[support]

Hello,

zedboard and zybo are larger because /dev/xillybus_smb and /dev/xillybus_audio logic?

Yes, it seems so.

As for the rest of your questions regarding porting to ZynqMP, you're unfortunately on your own. It might work out, it might not, I have no idea what the obstacles could possibly be.

What I tried to say in my previous answer is that it's probably not going to be easy at all. With emphasis on "probably", because I can't comment on a task I haven't even remotely tried myself.

Regards,
Eli