Hello,
Changes made in the processor's configuration (enabling SPI in your case) require a rebuild of the FSBL and hence also the boot.bin. The way that the processor is informed on how it should treat its I/O wires is through software configuration setting registers, which is done by the FSBL.
As the original FSBL was built in the ISE suite, the recommended flow for obtaining a new one is to make the changes in XPS (part of the ISE suite) and build the FSBL file using the SDK attached to XPS. The processor's configuration in the files for Vivado is not accurate enough for rebuilding FSBL.
As for creating the boot.bin file, the u-boot binary used in Xillinux-1.3 can be downloaded from this link:
http://xillybus.com/downloads/u-boot-xi ... .3.elf.zipIf you want to rebuild U-boot yourself, please refer to /usr/src/xillinux/uboot-patches/README.TXT in Xillinux distribution's file system for how to obtain the sources used to compile U-boot for Xillinux. It's recommended to use Xilinx' cross compiler for this.
Regards,
Eli