Zybo Xillybus open halt

Questions and discussions about Xillinux

Open Halt

Postby Guest »

Hi Everyone
I am use the Xillybus for test, and the load log is
Code: Select all
[    1.341558] usbcore: registered new interface driver usbhid
[    1.349260] usbhid: USB HID core driver
[    1.387222] mmc0: new SDHC card at address 0001
[    1.395328] mmcblk0: mmc0:0001 SD8GB 7.28 GiB
[    1.407370]  mmcblk0: p1
[color=#FF0000][    1.589513] xillybus_of 50000000.xillybus_ip: Created 3 device files.[/color]
[    1.603411] TCP: cubic registered
[    1.606656] NET: Registered protocol family 17
[    1.611578] Registering SWP/SWPB emulation handler
[    1.618917] regulator-dummy: disabling
[    1.623417] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[    1.759928] IP-Config: Complete:
[    1.763085]      device=eth0, hwaddr=1e:55:03:50:c4:42, ipaddr=, mask=

so, we can find the device is dev
Code: Select all
/dev # ls
console             network_throughput  tty16               tty47
cpu_dma_latency     null                tty17               tty48
full                port                tty18               tty49
i2c                 psaux               tty19               tty5
input               ptmx                tty2                tty50
kmsg                pts                 tty20               tty51
loop-control        ram0                tty21               tty52
loop0               ram1                tty22               tty53
loop1               ram10               tty23               tty54
loop2               ram11               tty24               tty55
loop3               ram12               tty25               tty56
loop4               ram13               tty26               tty57
loop5               ram14               tty27               tty58
loop6               ram15               tty28               tty59
loop7               ram2                tty29               tty6
mem                 ram3                tty3                tty60
mmcblk0             ram4                tty30               tty61
mmcblk0p1           ram5                tty31               tty62
mtd0                ram6                tty32               tty63
mtd0ro              ram7                tty33               tty7
mtd1                ram8                tty34               tty8
mtd1ro              ram9                tty35               tty9
mtd2                random              tty36               ttyPS0
mtd2ro              root                tty37               urandom
mtd3                snd                 tty38               vcs
mtd3ro              tty                 tty39               vcs1
mtd4                tty0                tty4                vcsa
mtd4ro              tty1                tty40               vcsa1
mtdblock0           tty10               tty41               vga_arbiter
mtdblock1           tty11               tty42               xdevcfg
mtdblock2           tty12               tty43              [color=#FF4000] xillybus_mem_8[/color]
mtdblock3           tty13               tty44              [color=#FF0000] xillybus_read_32[/color]
mtdblock4           tty14               tty45              [color=#FF0000] xillybus_write_32[/color]
network_latency     tty15               tty46               zero
/dev #

Zybo Xillybus open halt

Postby Guest »

Hi everyone
we use the xillybus to demo, we can find the device
and we write the application code
Code: Select all
int main()
   int fd, rc;
   printf("open start\n");
   fd = open("/dev/xillybus_mem_8", O_RDONLY);
   printf("open end\n");
   if (fd < 0)
      perror("Failed to open devfile");
   char buf[2048];
   ::memset(buf, 0, 2048);
   printf("read start\n");
   int rSize = ::read(fd, buf, O_RDONLY);
   printf("read end\n");
   if(rSize < 0)
      printf("rSize = %d\n", rSize);
      return 0;

   for(int y=0; y<2048/4 / 16; y++)
      for(int x=0; x<16; x++)
         printf("%d ", buf[y*16 + x]);

   return 0;

when the appilcation run

the system halt at after output the "open start", why ?

Re: Zybo Xillybus open halt

Postby support »


To begin with, I see only three devices files, so I assume you're using a custom IP core. Otherwise, it's quite peculiar why there are only three.

As for the I/O problem, I suggest taking a look on the Xillybus host application programming guide for Linux, on the web site's Documentation part:

http://xillybus.com/downloads/doc/xilly ... _linux.pdf

Section 3.2 discusses the best practices for reading data (which are in principle the common UNIX practices).

Looking at your code, you're using the C++ ::read() method mixed with a non-C++ open(), and it's not clear why you're passing it the O_RDONLY argument. I'm a bit surprised it even compiled.

It doesn't look like you're going to do a lot of C++ magic, so I suggest sticking to the plain C API. And follow the programming guidelines.

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