Instantiating <something> from unknown module <something els

[Guest]

Hi Everyone,

I have completed all the tutorials at the Xillybus portal. Following the steps in Xillybus tutorials: FPGA coprocessing for C/C++ programmers (part V) has not resolved this issue.

I modified the C code into a simple matrix multiplication logic as below:

Code: Select all

  // Matrix Multiplication
  for(i = 0; i < 3; i++) {
     // Iterate over the columns of the B matrix
     for(j = 0; j < 1; j++) {
        ycbcr[i][j] = 0;
        // Do the inner product of a row of A and col of B
        for(k = 0; k < 3; k++) {
           ycbcr[i][j] += 1 * rgb[k][j];
        }
     }
  }


You can ignore the logic for now, just a random multiplier of 1 for debugging purposes.

After a successful synthesis in Vivado HLS, the V files are imported into a fresh ISE project provided by Xillydemo bundle. The loopback is edited as in the tutorial to interface with logic instead of looping back the data. When i attempt to generate the new programming file, I get the following error:

Code: Select all

ERROR:HDLCompiler:1654 - "D:/Dropbox/FYP/Moving_Forward/hls-starter-1.0/coprocess/example/syn/verilog/xillybus_wrapper_sitofp_32ns_32_6.v" Line 33: Instantiating <xillybus_wrapper_ap_sitofp_4_no_dsp_u> from unknown module <xillybus_wrapper_ap_sitofp_4_no_dsp>


When I review the .V files generated by Vivado HLS, there is indeed no xillybus_wrapper_ap_sitofp_4_no_dsp_u.v file generated. The closest thing i could find was a "xillybus_wrapper_sitofp_32ns_32_6.v" file which is where the code for instantiating the unknown module resides.

Removing the matrix multiplication code solves this( I pass the input matrix values out without any manipulation) removes the error i faced.

Was hoping someone could shed some light on the issue I've been facing.

Thanks

[support]

Hi,

I'm not an expert on HLS, but I suspect that the problem lies in the two-dimensional matrices. It's a trivial concept in C, but under the hood, a two dimensional matrix involves an array of pointers to pointers. This isn't the most HLS-friendly concept.

So I would suggest trying to replace any X[i][j] with something in the style of X[i*ROWSIZE+j] and see if this helps.

Regards,
Eli

[Guest]

Hi Eli,

Thanks for responding to my question.

I have removed the matrices in question and have simplified the code somewhat:

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 uint32_t x1;
 float f1;
 uint32_t y1;

 xilly_puts("Hello, world\n");

 x1 = *in++;

f1 = *((float *) &x1);
y1 = *((uint32_t *) &f1);

  *out++ = y1;


Code: Select all

f1 = f1 * 0.1f;


The first block of code runs fine, however once the float multiplication is added I face the same error.

Upon further probing, I noticed that the "coprocess\example\syn\verilog" folder would contain the "xillybus_wrapper_fmul_32ns_32ns_32_4_max_dsp.v" but the module to be instantiated from within that (xillybus_wrapper_ap_fmul_2_max_dsp_ip.v) was produced as a .tcl file instead "xillybus_wrapper_ap_fmul_2_max_dsp_ip.tcl". I am guessing I need to generate the xillybus_wrapper_ap_fmul_2_max_dsp_ip.v file through other means with the provided .tcl file.

Granted this is not exactly a Xillybus related issue, I shall try posting this on the Xillinx forums instead and report back here for the benefit of others. However, I still welcome anyone who has light to shed on this.