Removing Debug Outputs: Implementation Error

[Guest]

After removing all xilly_puts() and xilly_decprints() from my HLS C code, I proceeded to remove the 3 debug signals as stated in tutorial: http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-4

Code: Select all

     .debug_ready(!debug_out_full || !user_r_read_8_open),
      .debug_out(debug_out_din),
      .debug_out_ap_vld(debug_out_write),

However, I am now getting the following critical warnings and errors:

Code: Select all

Synthesis
[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[7]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[6]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[5]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[4]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[3]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[2]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[1]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin din[0]

[Synth 8-4442] BlackBox module fifo_8 has unconnected pin wr_en

Implementation
Opt Design
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1.

[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I2, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/ram_full_i_i_1.

[support]

Hello,

The said tutorial was written before building the Verilog part with Vivado was possible, so it assumes that ISE is used. This partly explains the error you present (you obviously use Vivado).

To the point: After you removed the debug stream, fifo_8 became redundant. Vivado seems to have messed up while optimizing out its logic elements, ending up with a chunk of logic it can't handle. I suggest trying to remove the instantiation of fifo_8 as well.

Regards,
Eli

[Guest]

I am having this same problem and wondering if removing the instantiation was the solution? And if so, do you have to remove all reference to fifo_8 in the xillydemo.v file?
I'm getting a different error (...missing a connection on input pin I0...) but same problem I would guess.

[support]

Hello,

It's not clear what you meant with removing all reference to the FIFO. It's only referred to by the instantiation. What could be left after it has been removed?

Regards,
Eli

[Guest]

Does one need to remove all the wire definitions and ports related to the signals for the xillybus_read_8 and write_8 as well as the definition of fifo_8? I guess its not clear to me exactly what constitutes the instantiation.

[support]

I see. The instantiation is this part:

Code: Select all

  fifo_8x2048 fifo_8
     (
      .clk(bus_clk),
      .srst(!user_r_read_8_open),
      .din(debug_out_din),
      .wr_en(debug_out_write),
      .rd_en(user_r_read_8_rden),
      .dout(user_r_read_8_data),
      .full(debug_out_full),
      .empty(user_r_read_8_empty)
      );


So this is the chunk that should be removed (assuming this is indeed the solution).

The pedantic way to remove an instantiation also includes removing any wires and registers that have become redundant, but not doing this probably just adds a few warnings during synthesis (there are hundreds of them anyhow). So I would try just removing the part shown above.

Regards,
Eli

[Guest]

Thank-you. Will try it.

[Guest]

This did not work. It gave the warning: could not find module 'fifo_8x2048'. XDC will not be read for any cell of this module, which seemed ok, but then failed on some new
versions of the previous error regarding LUT4 cell, pins I0 and I2, and referencing xillybus_ins/xillybus_core_ins/unitw_3_ins/unitw_3_effective_rden1, unitw_3_effective_rden_AND_255_01, unitw_3_wr_request_condition_SWO. Perhaps I did not start far enough back in the sequence. I only redid the hls systhesis and the vivado steps.

[support]

Hi,

It's not clear why Vivado was looking for fifo_8x2048 if you removed its instantiation. It's even less clear why it was looking for it. At what stage was is missed? Synthesis? By the placer?

And a general note -- it's better to copy-paste errors made by the tool than describing them. Sometimes there are subtle details that get missed otherwise.

Regards,
Eli

[Guest]

Thanks for your help, but can work around by just printing out one character at the beginning of the code to be hls'd. That seems to satisfy the beast so am going to abort the effort to remove the debugging completely.

Agree about cut and paste of full errors, but am on unconnected machines at the moment. Thanks again for your time.