by Guest »
Hi Eli,
Yes, by high performance, I mean high bandwidth. My intention is to reduce the latencies in the Xillybus IP core and transfer the results from the FPGA to the host as fast as possible.
The FPGA logic is running at 100MHz frequency, so I need an interface that can transfer 32 bits of data to and fro for every 10ns i.e., 64Mbps.
Right now, I am running xillinux on Xilinx 7Z010 Zybo platform. Here both host and FPGA will be the Zybo itself.
I have one idea in my mind, Please let me know if its possible or not. As I am designing an accelerator I also need an interrupt signal which will be constantly monitored in the host. When the interrupt goes high, I will read the results and will continue further processing.
Also, I got pieces of advice to work on interfacing full AXI stream or AXI Accelerator adaptor. But, I have no idea on how complicated they are to implement. Please provide me some insights on this.
Also, If you have a better idea, Please share with me, it will be very useful for my application.
Thanks,
Raja