Hello,
I am sorry for my beginner question. I am new in the FPGA world - but I would like to know what is the minimal configuration for the custom IP.
I have generated the custom Xillybus IP. Now I want to add it to the Zynq-based design in Vivado. I need only to stream data from the PS to PL, nothing more.
One stream is enough for me. I am not sure what else (what IP cores) I have to add to the design to make one stream from the PS to PL work.
I tried to look at the Xillybus reference design but it seems that there is much more that I need and I get confused from this complex design.
Can someone write me the steps needed to implement the Xillybus custom IP to the Zynq design, please?
For the moment, I have made the following steps:
1) Generated Xillybus custom IP and download it
2) Created a new Vivado project (VHDL)
3) Created design and set Zynq processing system parameters for my board
4) Added the custom Xillybus IP Core to the design and run connection automation
5) What else? I do not know what I have to add and what to do further...Add a FIFO? If yes, is there some FIFO IP Core working with Xillybus or I have to write some in VHDL? The IP Core has still the following ports unconnected:
- to_host_fpgahost
- ap_clk
- bus_rst_n
- m_axi
- from_host-write_32
- GPIO_LED[3:0]
- host_interrupt
- quiesce
- to_host_fpgahost_open
- from_host_write_32_open
Thank you in advance for every advices.
Jirka