Hi all,
I've got a question about the Memory Write Request TLP with Data Payload and 32-bit addressing.
On the tutorial guide Part I it's an example of MWr and Data Payload are placed in DW 3 (unaligned data).
While Altera for their Stratix V claims that this DW 3 is reserved (Appendix A, TLP Packet Format with Data Payload of "Stratix V Hard IP for PCI Express User Guide" - https://www.altera.com/zh_CN/pdfs/literature/ug/ug_s5_pcie.pdf , page 325).
I'm using 256-bit mode with Avalon-ST interface.
Could you please explain me when I can use 3DW header with unaligned data for 256-bit Mem Request?
Thanks,
Dave