Capture example (async FIFO) on Kintex-7?

[jmansour]

Hi,

I would like to follow the data capture example with my Kintex-7 board. I have been integrating the code from xillycapture.v in my xillydemo.v, and have found that synthesis fails. The (first) reason is that xillycapture.v has:

Code: Select all

   async_fifo_32 fifo_32
     (
      .rst(!user_r_read_32_open),
      .wr_clk(capture_clk),
      .rd_clk(bus_clk),
      .din(capture_data),
      .wr_en(capture_en),
      .rd_en(user_r_read_32_rden),
      .dout(user_r_read_32_data),
      .full(capture_full),
      .empty(user_r_read_32_empty)
      );


whereas xillydemo.v has different properties (e.g. srst instead of rst):

Code: Select all

   fifo_32x512 fifo_32
   (
     .clk   ( bus_clk              ),
     .srst  ( tst_data_reset       ),
     .din   ( tst_data_in          ),
     .wr_en ( tst_data_wren        ),
     .rd_en ( tst_data_rden        ),
     .dout  ( user_r_read_32_data  ),
     .full  ( user_w_write_32_full ),
     .empty ( user_r_read_32_empty )
   );

I couldn't find how to add an async fifo to my project. I thought this might be done by generating a custom IP core, but even though my fifo is specified as asynchronous, there is no .xco file. The async_fifo_32.xco in the xillycapture example is configured for a Spartan6 board. There seems to be a GUI in Vivado to customize FIFOs, however I am not experienced with FPGA programming, and I am not sure this is the right solution. Any ideas how to get an async FIFO working on Kintex-7 (or this capture example in general)?

(The reason I want to use an async FIFO is, I already have got a simple data generator over xillybus_read_32 running, however I frequently loose data after a while - e.g. a counter skips some numbers. Also, at some point we want to capture from a data source with a different clock (somebody more experienced than I will implement that I'm just exploring and learning right now). I read that in both cases the async model is advantageous. Does that make sense, or am I on the wrong path here?)

[jmansour]

Just a quick self-answer, I was able to generate a FIFO using the built-in FIFO Generator in Vivado (in the IP catalog). The properties in the .xco file all map to properties in the wizard, and the generated FIFO works as expected. (Just have to find out now how to make the generated files work with version control but I've already seen there is a document about that.)

[support]

Hello,

It's good you got it sorted out.

Just a comment on terminology:

• Async FIFO: FIFO with two clocks.
• Async Xillybus stream: Allowing data to flow between the FPGA and host, also when there's no current read() or write() call on the host (whichever applies).

Two completely different things...

Regards,
Eli