Hi, dear support,
We use the Xillybus lite in demo bundle for register access and it works in Zybo. However, due to have a 32 bits wide with 1K depth register file added, we utilize a register address as FIFO pointer to interface to a BRAM with 32 by 1024 bit.
But we encountered a issue, for example, write A5A5A5A5 and 5A5A5A5A in sequence to the BRAM via the FIFO pointer address over Xillybus lite and get A5A5A500, 5A5A5AA5, A5A5A55A, etc. It seems that bit 7:0 is delayed by 1T. Thus, I have the following questions.
I am not sure if we can implement FIFO pointer r/w over Xillybus lite in demo bundle. Another question is can the Xillybus lite of demo bundle 2.0a support 8kB memory map or only 4kB.
Finally, does it related to cache setting since the test code only write the same address for 1024 times and then read the same address for 1024 times ? The BRAM will be access by other ip with random read access and then we cannot use the Xillybus bus ip FIFO.
All the best,
thanks