Hi all,
In my project, I am trying to connect the Xilinx Virtex707 evaluation board to the Nvidia Jetson TX1 through PCIe.
I used you’re the xillybus PIe IP for the communication.
I configured the FPGA with demo design in xillybus-eval-virtex7-2.0c.zip.
And ran the following c code snippet to measure the round-trip time for the stream ports in the loopback configuration.
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unsigned int DataWrite = 123;
unsigned int DataRead;
write(fdw32, (void *) DataWrite, sizeof(unsigned int));
read (fdr32, (void *) DataRead, sizeof(unsigned int));
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My measurement shows about 11msec for both write and read operation.
I am wondering if there is a technique to reduce this time to about a couple of micro-second.
Note that I am trying to send command and receive acknowledge using this write and read. So, at this step, my goal is not sending a huge amount of data to FPGA.
Thanks