I get this question a every now and then, so I thought I should put a post here, just in case someone is in a similar situation.
This is relevant only for Xilinx FPGAs with Gen3 or later. That means all Ultrascale devices and later + some of Virtex-7.
It's also relevant only if you've made manipulations to Xilinx' PCIe block, or set up one from scratch. If you rely on the PCIe block in the demo bundle, without any change, this isn't for you.
What you'll see, more or less: All upstream communication (streams from the FPGA to host) works perfectly. But when writing towards the FPGA, it works a few times, and then after about 10-15 write() operations, it gets stuck: write() doesn't return, but it's still possible to terminate the program normally with CTRL-C. But when trying to run the program again, write() will get stuck from the first attempt. Rebooting the computer will not make any difference. Only reprogramming the FPGA.
The problem + solution: In the demo bundle, the PCIe block is configured with the "Enable Client Tag" feature enabled. This is a checkbox in the "Basic" tab of the GUI wizard. Some people forget to enable this feature when they create a new PCIe block, or turn it off by mistake. So check the checkbox, reimplement the project. That's it.
This thing with "Enable Client Tag" exists only in Xilinx' PCIe block with RQ/RC/CQ/CC interface, i.e. Xilinx' block that support Gen3 and later. Don't look for it in previous FPGAs.
Hope this helps someone out there.
Eli