by support »
Hi,
If you're in the business of actually generating TLP packets, you're most likely writing HDL code to be implemented to be a bitstream for an FPGA or silicon on an ASIC. If you're wearing that hat, you'll have an IP core (the logic world's library function) to work with. That IP core's specification tells you exactly how to communicate the information about the packet to be transmitted. For exampe, Xilinx will ask you to form it as an AXI stream packet. Altera will tell you to use their Avalon interface.
Those interfaces have wires that are separate from the data wires (plus quite a few other control wires). The common way is to indicate the last clock containing data for a specific packet by asserting a wire saying called something like "end of packet". That will make the PCIe controller begin handling the packet
If you're just running software, a packet is created when a PCIe-enabled processor issues a read or write request on the bus. In that case, you don't have anything to do with the packet formation. You just perform a read or write access to say, memory space, and the packet is generated automatically by the processor's logic.
I hope this clarified things.
Eli