Hi,
dbakoyiannis wrote:Hello again,
What I understand is that when the three signals that you mention (s_axis_tx_tready, s_axis_tx_tvalid, s_axis_tx_tlast) are asserted this means that there is a TLP.
Well, sort of. When these signals are high together, the last element of the TLP is present on the tdata wires. Since each TLP has one such last element, counting these events counts the TLPs.
If you want to gather the TLP information, I suggest connecting the tdata (or rdata) wires to the data input ports of a FIFO. The FIFO's write enable should be (s_axis_tx_tready && s_axis_tx_tvalid). As a result, each element in the bus is written to the FIFO.
You probably want to connect the tlast wire as well, possibly concatenated with the data word, so the boundaries between the packets are logged. But it's possible to do without these, as the length of the packets can be deduced from the TLP's headers.
How to get the FIFO's content handy is a different topic. I used a Xillybus stream to transport its content to a PC (which is very easy). As Xillybus' traffic caused TLP traffic, I ended up with a system that sniffs its own traffic, but that was fine for the purpose of exploring what's going on.
Regards,
Eli