by support »
Hello,
There's nothing in those changes that should prevent things from working properly, however sometimes making them causes a mistake, and that's when things break. So I would suggest trying to the original bundle, with the absolutely minimal changes possible. There is no problem leaving the link as x8, and have the upper 4 lanes connected to nothing in particular. The PCIe block negotiates the link width with the host, based upon what's connected. Hopefully that will work, and then it's a matter of gradually changing a working project to the desired target.
Having said that, it's quite unusual that the PCIe device is detected and then not works properly. Maybe some mishap while connecting the ILA to the FIFOs' ports?
And once again -- you did type something in the DOS windows running xillybus_write_8 and pressed ENTER...?
Also, I didn't complete understand this:
mim wrote:Actually the Timing stack (TNS) is negative (
) about -0.258 while THS is not.
If you were referring to timing slack, and it was negative, it means that the design didn't meet timing constraints, in which case anything can happen. There's a Tcl script (showstopper.tcl) in the project that is supposed to prevent you from generating a bitstream file if this is indeed the case. So it's not clear what you meant with that.
Regards,
Eli
Hello,
There's nothing in those changes that should prevent things from working properly, however sometimes making them causes a mistake, and that's when things break. So I would suggest trying to the original bundle, with the absolutely minimal changes possible. There is no problem leaving the link as x8, and have the upper 4 lanes connected to nothing in particular. The PCIe block negotiates the link width with the host, based upon what's connected. Hopefully that will work, and then it's a matter of gradually changing a working project to the desired target.
Having said that, it's quite unusual that the PCIe device is detected and then not works properly. Maybe some mishap while connecting the ILA to the FIFOs' ports?
And once again -- you did type something in the DOS windows running xillybus_write_8 and pressed ENTER...?
Also, I didn't complete understand this:
[quote="mim"]
Actually the Timing stack (TNS) is negative ( :D ) about -0.258 while THS is not.[/quote]
If you were referring to timing slack, and it was negative, it means that the design didn't meet timing constraints, in which case anything can happen. There's a Tcl script (showstopper.tcl) in the project that is supposed to prevent you from generating a bitstream file if this is indeed the case. So it's not clear what you meant with that.
Regards,
Eli