by support »
Hello,
There should be no data missing at all. If the FIFO's "full" port is connected to the Xillybus IP core as in the demo bundle's example, Xillybus will stop writing to the FIFO once it gets full, and resume writing when there's room again. So all data that was sent from the host will appear at the FIFO's read end, no matter how slow or fast it's read, or the size of the chunks it was written in. When properly connected, no data is lost, ever.
Attempting to slow down bus_clk would probably not solve the problem anyhow, by the way. I can see mainly three possibilities for your problem:
(1) The FIFO isn't connected properly to Xillybus' IP core (in particular, bus_clk to wr_clk and "full" to Xillybus' respective full signal)
(2) The logic loses the data while reading it (for example, rd_en tied high when data isn't accessed)
(3) The data wasn't written completely on the host. For example, write() may write less byte than the required by its call arguments. Always check its return value for how much data was actually written.
I hope this gave a direction.
Regards,
Eli