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Why the PCIE_TX_N and PCIE_TX_P are 8 bits
Questions and discussions about the Xillybus IP core and drivers
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Re: Why the PCIE_TX_N and PCIE_TX_P are 8 bits
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Guest
»
Yeah, indeed. And I just test this can be easily used with python with:
`xillybus_write_32.write(buf)`
`xillybus_read_32.read(size_of_buf)`
Eli, thanks for the Fantastic IP and fantastic guidance! I really appreciate it!
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