support wrote:Hello,
If the neither the empty signal nor the data input change as a result of the read cycle, the rd_en signal can indeed be ignored. So controlling the empty signal only based upon _addr_update will do the work, however you won't be able to read more than a single memory cell this way.
Regards,
Eli
in some applicaiton, if i want to use the the mem_intf bridge to axi4 lite to read and write reigister, is it possible?
host : lseek + write -> addr + wdata
host: lseek + read -> addr + rdata
write : i can use wren and the full to delay , if i capture wren i can active full to high ,only pull low when axi lite write done
read: i want to use addr_update,but when lseek + write in host also generate addr_update? is it any method to solve it?