Hello,
I am using Xillybus for Zedboard. I am trying to implement serial TX/RX communication for which I would like to use JA PMOD connector on ZedBoard. Unfortunately for me, JA PMOD is already used as an EMIO GPIO in Zynq PS, so I decided to edit Zynq PS IP core to use only 54 EMIO GPIO ports (instead of default 56).
I have edited system.v and xillybus.v sources (from upper hierarchy) to accommodate vector of size 54 instead of 56 and I have edited constraints in which I removed PS_GPIO[54] and PS_GPIO[55] pin location declarations.
I decided to assign my RX to Y11 location, which was assigned to PS_GPIO[24], and my TX to AA11 location, which was assigned to PS_GPIO[25].
I assigned U6 and U5 locations to PS_GPIO[24] and [25], which were assigned to now removed signals PS_GPIO[54] and [55].
I get critical warnings during synthesis saying "Cannot set LOC property of ports, loc is blocked" which points to my TX and RX signal declarations in XDC file.
Synthesis and implementation design runs complete successfully but bitstream generation fails due to "unconstrained ports" (UCIO-1).
I'm running in circles trying to resolve this problem, I've tried using I/O planning and fixing ports which assignes my TX and RX signals to FMC which is unacceptable. Please help.
Best regards,
kresica