Hi,
I am using stream read and write to tranfer files from host PC, process in the FPGA and send the data back.
In my project, an ILA is used to monitor the control signals from host pc to my fpga. However, sometimes the user_rd_en never raise even there is data in the read fifo of PC. And I also see user_rd_open keeps high even after I close the device file from the terminal. What could be the reason for this problem?
I wonder how the user_rd_en and user_wr_en generated? And is there any method in the host pc program that we can directly control these signals?
Greatly appreciate for any help in advance!
Thanks,
Mandy