- I've previously gotten the xillybus demo fully working on the KC705
- My target board PCIe is 4-lane, not 8-lane
- I've gotten the Xilinx PCIe demo working on my board at 4 lanes. This includes moving pcie lane, pcie clock, and pcie reset signals to non-standard pin locations used by the custom board.
- Note that I have the working Xilinx PCIe demo in my config flash. I must cold start (with jtag usb cable removed from PC), in order for BIOS to enumerate PCIe bus. After that, I can jtag/config a new bitstream and simply warm boot my linux host.
- I have a VIO in there. It shows me the link up signal. (The Xilinx PCIe demo has an active high link up signal, while the Xillybus demo has an active low link up signal.)
- I can re-jtag/re-config the same Xilinx PCIe demo bitstream. At first, the VIO shows the link is NOT up. This is expected because I momentarily broke the PCIe connection with the host. I warm start the linux host. The VIO immediately shows the link IS up. A minute later I can log in to linux host and lspci shows my custom board. Remember, this is using the Xilinx PCIe demo bitstream. (No driver yet.)
- I am having trouble getting the xillybus demo fully working on my custom board at 4 lanes.
- I made what I believed to be the correct changes to go down from 8 to 4 lanes. This included editing xillybus.v (now xillybus_4x.v), pcie_k7_8x.v (now pcie_k7_4x.v), and reconfiguring ip pcie_k7_vivado (now pcie_k7_vivado_4x). It also included moving those pin locations.
- FAILED as follows
- When I jtag/config this xillydemo bitstream, the VIO shows me that the link is NOT up, as expected. Then I warm boot my linux host. The VIO very quickly shows me that the link is up, as expected and so far so good.
- However, the linux host won't boot further. It's hung somehow. I believe it's hung in the BIOS, but I'm not certain. So the VIO says the link is up, but the system linux host boot correctly.
- So now I try replacing the lower level portions of the xillydemo with the lower level portions of the Xilinx PCIe demo. Maybe there's a snafu in something I did. I'm copying low level modules from a working project to a non-working project. I replaced the actual Xilinx PCIe IP (pcie_k7_vivado_4x.xci replaced by pcie_7x_0.xci) and also the pipe_clock module (pcie_k7_vivado_pipe_clock.v replaced by pcie_7x_0_pipe_clock.v).
- FAILS in the same way
- It seems like the only difference in the two projects now is at the FPGA "application" level. That is, the Xilinx PCIe demo is using a Xilinx-provided pcie_app_7x.v, while the modified xillydemo is using xillybus_core.v as well as top level logic.
- I wondered if the xillybus_core needed to be different for x4 lane operation instead of x8 lane operation, but I see no such setting in the IP Factory. (This is Kintex-7, of course, just like KC705.)
- Note that when I replaced pcie_k7_vivado_pipe_clock.v with pcie_7x_0_pipe_clock.v, I saw differences in the parameters provided. PCIE_LINK_SPEED changed from 3 to 2. PCIE_USERCLK1_FREQ and PCIE_USERCLK2_FREQ want to change as well, but I left them at the xillydemo values of 4 because the Xilinx PCIe demo code was a bit obtuse and I didn't want to get it wrong.
- I made what I believed to be the correct changes to go down from 8 to 4 lanes. This included editing xillybus.v (now xillybus_4x.v), pcie_k7_8x.v (now pcie_k7_4x.v), and reconfiguring ip pcie_k7_vivado (now pcie_k7_vivado_4x). It also included moving those pin locations.
Your suggestions are GREATLY appreciated!
Thanks,
Helmut