Hi all, I am a newbie to embedded computing. I installed Xillinux1.1 in my ZedBoard and connected my logic design to Xillybus through the application FIFOs. A C project is also created for talking to the FPGA through the device files( xilllybus_read_32 and xillybus_write_32) . My logic design is for a halftoning algorithm. So far the prototyping has been completed and the testing results are satisfying. However, I am still confused about the xillybus architecture and its transport mechanism. The questions accumulated are listed as below.
1. In XPS, the xillybus IP core is instantiated in the PL. In ISE, there is another module called xillybus_core. I assume the xillybus IP in XPS is a PCIe IP with AXI interface while the xillybus_core in ISE packs and depacks the TLPs. Is my understanding correct?
2. I am not much into DMA. But at least, there should be a DMA controller for DMA. In XPS, the DMA controller( the green block named after "DMA8 Channel") seems not enabled (none of its interfaces are enabled). Where is the actual DMA controller for xiilybus loacted?
3.Is there any documentation specifying how the host driver works? I tried to read the driver source code xillybus.c. But it is too hard for me to understand such a complicated project. I am eager to know how the driver switches on/off the DMA transfer.
4. There is an interrupt from Xillybus to the host. When will the XIllybus trigger the interrupt? Is the interrupt handler included in the host driver?
5. Also there is another interrupt from the host to the Xillybus? When will the host trigger this interrupt? How does Xillybus respond?
6. I use plain read()/write() to send/receive data. My code follows the template of the C code example from http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-2. A typical loop used in the C code is like the following :
while (donebytes < sizeof(struct packet) * N) {
rc = write(fdw, buf + donebytes, sizeof(struct packet) * N - donebytes);
if ((rc < 0) && (errno == EINTR))
continue;
if (rc <= 0) {
perror("write() failed");
exit(1);
}
donebytes += rc;
}
We keep doing read()/write() in a loop until the desired number of bytes is transferred. I am curious about when a single read()/write() returns? Take write() for instance, does it return when the DMA buffers are full?
7. When read() is called and the FPGA cannot send any data in response (the FIFO is empty), it seems that the current thread pauses until the arrivals of the data. Why could such a pause happen?
I am looking forward to any response regarding these questions. Thank you in advance.