Hi ,
PCI/PCIE Config space Type 1 header has 2 BARs in it. Whenever a Downstream routed packet is received on the primary link of Switch Upstream port, it checks if the packet is intended for the US port itself(Checking against 2 BARs of T1 header) or secondary Link ports( Checking against the Base/Limit Registers).
I can't figure out when any SW US port will be targeted with a Memory Read/Write packet? Does a SW US port contain the memory(I dont think so)?
Regards,
Vismay