Hi,
I'm new to FPGA and have no experience of HDL. I'm trying the bundle demo for Xilinx KCU105 Board with Vivado 2017.3.
I'm following the Xillybus demo guide with using blockdesign. The "Generate Bitstream" shows the following error:
ERROR: [Synth 8-448] named port connection 'cfg_ext_read_data' does not exist for instance 'pcie' of module 'pcie_ku' [/home/x29yan/workspace/fpga/xillybus/xillybus-eval-kintexultrascale-2.0a/blockdesign/blockdesign/ipshared/46fa/src/xillybus_block.v:421]
ERROR: [Synth 8-448] named port connection 'cfg_ext_read_data_valid' does not exist for instance 'pcie' of module 'pcie_ku' [/home/x29yan/workspace/fpga/xillybus/xillybus-eval-kintexultrascale-2.0a/blockdesign/blockdesign/ipshared/46fa/src/xillybus_block.v:422]