by support »
Hello,
I understand that you want to run in an 1x configuration rather than Virtex 6's default of 4x. I suggest requesting a demo bundle for 1x directly through email.
But I'll explain the principle for the sake of understanding:
The Xillybus IP core relies on the PCIe front end from Xilinx (or Altera for their FPGAs). The number of lanes should be changed in the front end core.
A direct consequence is that the number of PCIe pins from the PCIe front end core is reduced. The xillybus.v and xillydemo modules should be edited to reduce the signals that connect these external pins with the PCIe core.
In some cases, there is a need to update the timing constraints and also remove some pin placements. The best way to tell is looking how the constraints file produced by Xilinx' PCIe core changes when the lane setting is changed from 4x to 1x.
Note that all of these changes have nothing to do with Xillybus itself.
Since the Xillybus IP core doesn't care what happens beyond the PCIe front end core, there is no problem configuring and downloading the regular Virtex-6 IP core. The only thing to keep in mind is that the actual allowed bandwidth is reduced to around 200 MB/s in each direction, as with Spartan-6.
If the host supports Gen2 PCIe, it's possible to achieve around 400 MB/s as well.
Hope this helped.
Eli