I think this document pretty much sums it up:
http://www.pcisig.com/specifications/pc ... _Limit.pdfThis message allows the host to change the maximal allowed power consumption of a endpoints, switches and bridges. The receiver copies some of the bits in the message's payload into it's device capabilities registers, and thus changes the allowed power.
I suggest referring to section 2.2.8.5 of the PCIe spec v1.1.
I hope this gave a hint.
Eli