Thank you very much for your three articles introducing PCIe. I have two questions:
Question 1 on why transfer rate as a function of amount of data transferred continues to improve even after going beyond maximum payload size: I understand the payload size request in the configuration register can be from 128 bytes to 4096 bytes in powers of two, and that the root complex informs all nodes of the maximum data payload (MDP). Suppose in some system the MDP happens to be 4 kB. If one plots the data transfer rate for various sizes, why doesn't the curve level off after 4 kB? Because even if 1000*4 kB needs to be transferred, it will be transferred as 1000 separate transfers of 4 kB each. So the question is: even though payloads have a maximum size of 4 kB, why do we see improved data transfer rates for transferring amounts larger than 4 kB?
Question 2 regarding "No end-to-end acknowledgment is ever made, and neither is it really necessary.": Consider the need for A to write to B and inform C when write has completed. C needs to know when all the data has arrived at B and B has "flushed its FIFOs" to DDR, and not just when A has finished sending out data. If A sends to B a 0-byte read from the very last write-address, and gets back the 0-byte data, is it guaranteed that B has flushed all data to DDR and so now is the right time for A to sent a MSI to C informing it of completion of the write?
Thanks.